Conventionally, in a SRAM semiconductor memory device, as shown in a circuit diagram of FIG. 1, each cell includes two access transistors M1 and M2 connected to the word line W/L and complementary bit lines B/L and /B/L. Access transistors M1 and M2 and driving transistors M3 and M4 are each composed of an NMOS transistor and load devices M5 and M6 are each composed of a PMOS transistor. In other words, a SRAM cell includes a latch having two inverters (M5 and M3 working as first inverters and M6 and M4 working as second inverters) and the access transistors M1 and M2.
The access transistor M1 is connected to the transistor M5, which is a load device, and the transistor M3, which is a driving transistor. The access transistor M2 is connected to the transistor M6, which is a load device, and the transistor M4, which is a driving transistor. A first cell node (a) of the access transistor M1 is connected to the gate of the driving transistor M4 connected to the access transistor M2. A second cell node (b) of the access transistor M2 is connected to the gate of the driving transistor M3 connected to the access transistor M1. When one cell is selected by the word lines and bit lines and the selected word line is on, a voltage of the cell node becomes high level or low level in accordance with a voltage of the bit line. Hence, writing and reading operations through the access transistor can be performed.
FIGS. 2a through 2d are views showing a fabrication of an access transistor in a SRAM memory cell. In the first step, as shown in FIG. 2a, a field oxide film 3 is formed at an element isolation region on a semiconductor substrate 1, resulting in the definition of a portion for an active region and a portion for an element isolation region, and a gate insulating film 5 is formed at the active region on the substrate.
In the second step, as shown in FIG. 2b, a buried contact 7 is formed by etching the gate insulating film 5 so that a predetermined portion of the substrate surface may be exposed in order to connect the gate of the driving transistor M3 with the second cell node (b). Thereafter, a poly-silicon film 9 is formed on the entire surface of the above-mentioned pattern. In order to dope an impurity into the poly-silicon film 9, an ion implantation is performed using POCL.sub.3, which is a high density n-type impurity. During the above process, a predetermined portion of the gate insulating film 5 is eliminated, and then the high density n-type impurity is doped into a predetermined portion of the exposed surface of the substrate, resulting in the formation of an n.sup.+ impurity region in the substrate of the buried contact 7.
In the third step, as shown in FIG. 2c, a gate 9' is formed by etching a predetermined portion of the poly-silicon film 9 and an n- lightly doped drain region 11 (hereinafter, called n- LDD region) in the substrate 1 is formed by an ion implantation of a low density n-type impurity, using the gate 9' as a mask. Continuously, the corresponding surface of the substrate 1 is allowed to be exposed by etching the gate insulating film 5 of the bit line side at which the buried contact 7 is not formed. After etching a predetermined thickness of the exposed surface of the substrate in the buried contact 7, a sidewall spacer 13 is formed at the side of the gate 9'.
During the fourth step, as shown in FIG. 2d, an n+ source/drain region is formed by an ion implantation of a high density of n-type impurity into the substrate. The gate 9' and the sidewall spacer 13 is used as a mask during the ion implantation.
An access transistor fabricated by the above-mentioned four step suffers from a loss of silicon in the process of forming the buried contact in order to connect the cell node of the access transistor and the gate of the driving transistor located in the opposite direction therefrom. Thus, a contact resistance of the cell node is increased, resulting in a reduction of the operational stability of the cell. Further, since a current flows in the access transistor irrespective of the voltage of the cell node, and is controlled only by the voltage of the word line, the access transistor connected to a low voltage level of the wordline W/L supplies as great an amount of current as the access transistor can supply, causing the voltage of the access transistor, coupled to the low voltage level, to be raised. The operational stability of the cell is greatly reduced.